The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that do not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Processor memory transactions are frequently characterized in locality, meaning that most reads and writes by a single processor to a main memory during a certain time frame are to memory locations that are clustered together within the main memory space. Because physical memory addresses are contiguous, processor transactions that are characterized in locality will result in a large number of memory transactions to memory addresses that are numerically close together, or clustered within a certain range of contiguous memory addresses (although the actual memory addresses of the individual memory transactions are not themselves necessarily contiguous, although they may be). Because memory data are allocated to cache lines (such as in system level cache) in which the cache lines have indexes that match the least significant bits of the memory addresses, data from memory transactions that are characterized in locality will tend to be allocated to cache lines that are also clustered together in cache lines within a range of contiguous indexes (although the actual indexes of the cache lines are not themselves necessarily contiguous, although they may be). An Asymmetric Multi-Processor (AMP) system is a multi-processor core system with a shared system level memory cache (such as an SL2 cache). In conventional AMP systems, needs of the different processor cores are accommodated by rigidly or flexibly partitioning the space in the system level cache.